1. Field of Invention
This invention relates to a method for improving the planarization of a dielectric layer in the fabrication of metallic interconnects, and more particularly to a dielectric planarization method employing rapid thermal processing (RTP) to achieve the high level of compaction desired for a dielectric layer.
2. Description of Related Art
In the production of metallic interconnects, the planarization of a dielectric layer is a very important part of the process. Owing to the good trench-filling capability of spin-on-glass (SOG) methods, it is generally accepted as the preferred method for local planarization.
FIGS. 1A through 1D are cross-sectional views showing the progression of manufacturing steps for the production of metallic interconnects using a conventional spin-on-glass method. First, referring to FIG. 1A, a substrate 10 with a MOS component already formed thereon is provided. The MOS component consists of source/drain regions 11 and gate region 12, with spacers 12a already formed on the sidewalls of the gate region 12 and with metal silicide layers 13, for example, titanium silicide (TiSi.sub.2), already formed on the surfaces of the source/drain regions 11 and the gate region 12. Then, a dielectric layer 14 is formed on the substrate surface 10. The dielectric layer 14 may be, for example, a borophosphosilicate glass layer formed by a chemical vapor deposition method. Next, a spin-on-glass layer 15 is coated onto the surface of the dielectric layer 14 by a spin-on-glass method. Subsequently, the spin-on-glass layer 15 is removed by an etch-back operation.
Thereafter, referring to FIG. 1B, a pattern is defined on the dielectric layer 14 to form contact windows 16 exposing the metal silicide layers 13 above the source/drain regions 11. Afterwards, a pre-metal etching (PME) operation is performed to remove a native oxide layer (not shown) formed as a result of open air contact with the exposed portions 20 of metal silicide layer 13.
Referring next to FIG. 1C, a barrier layer 17, for example, a titanium/titanium nitride (Ti/TiN) layer, is formed over the dielectric layer 14 and the exposed portions of the metal silicide layer 13. Thereafter, a tungsten layer 18 is formed over the barrier layer 17 to fill completely the contact windows 16.
Finally, referring to FIG. 1D, the tungsten layer 18 is anisotropically etched back to form tungsten plugs using the barrier layer 17 as an etching stop layer. Lastly, a metallic layer 19, for example, an aluminum layer, is formed over the barrier layer 17 and the tungsten layer 18. Subsequently, a pattern is defined on the metallic layer 19 to complete the formation of the metallic interconnects.
In the aforementioned conventional method of fabricating metallic interconnects, owing to the presence of metal silicide layers on the surface of the source/drain regions for the lowering of contact resistance, a pre-metal etching (PME) operation is necessary after the formation of the contact windows. However, this pre-metal etching operation causes damage to the exposed surface 21 of the dielectric layer 14 in the form of voids and miniature fissures. FIG. 2 shows a picture taken by a scanning electron microscope (SEM) of the surface 21 of the dielectric layer 14 after a PME operation. Later in the process, when metallic tungsten is deposited, some of the metallic tungsten may seep into the fissures, and although there is a subsequent etching back operation, the in-filled tungsten in the fissures is rarely removed, and so metallic tungsten stringers may be left behind. FIG. 3 shows a picture taken by the scanning electron microscope (SEM) of the surface 21 of the dielectric layer 14 after the etching back of the metallic tungsten layer 18. As a result of the residual metallic tungsten still occupying the space within the fissures, short circuiting paths may be established with the subsequently deposited metallic wiring.